1. Field
Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same.
2. Description of the Related Art
Semiconductor memory devices may be classified as volatile memory devices or nonvolatile memory devices. The volatile memory devices (e.g., a dynamic random access memory (DRAM) and/or a static random access memory (SRAM)) may input and output data at a relatively high speed, but lose the stored data when power is interrupted. The nonvolatile memory devices may retain the stored data even though the power is interrupted.
A flash memory device is a nonvolatile memory device and may be a highly integrated device having both an erasable programmable read only memory (EPROM) and an electrically erasable programmable read only memory (EEPROM). The flash memory devices may be classified into a floating gate type flash memory device and a floating trap type flash memory device according to the type of data storage layer in a unit cell.
The floating trap type flash memory device may store electrical charges in a trap formed in a nonconductive charge trap layer, whereas the floating gate type flash memory device may store electrical charges in a polysilicon layer. A memory cell of the floating trap type memory device may include a gate structure of a tunnel oxide layer, a silicon nitride layer serving as a charge trap layer, a blocking oxide layer and/or a conductive layer on a silicon substrate.
FIG. 1 is a diagram illustrating a conventional nonvolatile memory device 10 of a silicon oxide nitride oxide semiconductor (SONOS) structure. Referring to FIG. 1, a memory cell of the memory device 10 may include an ONO layer 15, including an oxide layer 12, a nitride layer 13 and an oxide layer 14, and polysilicon 16, which may be formed in a channel region 18 defined between source/drain regions 17 formed on a substrate 11. The memory cell may have a single bit structure indicating logic state “0” or “1” according to existence or nonexistence of electrical charges trapped in the nitride layer 13 of the ONO layer 15. There may be a demand for a memory device that has an increased data storage capacity so that more than two logic states may be indicated, without increasing the size of the memory device. As nano technology has been developed, nonvolatile memory devices, using nano crystals, have been studied.
FIGS. 2 and 3 are diagrams illustrating a conventional nonvolatile memory device using nano crystal. Referring to FIG. 2, a channel region 28 may be disposed between source/drain regions 27 formed on a substrate 21. A memory cell may include a memory layer 25 and a gate electrode 26 formed on the channel region 28. The memory layer 25 may include a tunnel oxide layer 22, a charge trap layer 23 and a blocking oxide layer 24. The charge trap layer 23 may include nano crystals 23NC of cluster and/or dot shape of several to several tens nm. Electrical charges injected into the nano crystals 23NC may not move easily between the nano crystals 23NC. Compared with the general memory device of the SONOS structure, the memory device using nano crystals may restrain the lateral diffusion of electrical charges and may be suitable to achieve the memory device of a multi bit structure.
In implementing the nonvolatile memory device using nano crystals as a multi-bit (e.g., about 2 bits per cell) nonvolatile memory device, there may be a limitation in scaling down the size of the memory device. Electrical charges may be locally injected into a charge trap layer close to the source/drain regions 27 in order to use the memory device with nano crystals as the multi-bit memory device. With a short-channel memory device, overlapping may occur when injecting electrical charges and the injected electrical charges may be laterally diffused, causing disturbance. The memory device may not achieve the 1 cell-2 bits operation. A channel length of the memory device may be maintained at more than a given length, but this may be contrary to a relatively high integration of the memory device. Therefore, the memory layer may be divided into two layers.
Referring to FIG. 3, source/drain regions 37 may be formed in a substrate 31. Two memory layers 35L and 35R, separated horizontally, may be disposed on a channel region 38 defined between the source/drain regions 37, with an insulating layer 35C being interposed therebetween. The memory layers 35L and 35R may each include tunnel oxide layers 32L and 32R, charge trap layers 33L and 33R, and blocking oxide layers 34L and 34R. A gate electrode 36 may be located on the memory devices 35L and 35R and the insulating layer 35C. The structure may scale down the memory device to a degree. Depending on the number of the nano crystal 33NC included in the charge trap layers 33L and 33R during scaling down, a threshold voltage shift may become large and degrade the reliability of the device.
FIG. 4A is a diagram illustrating a charge storage layer in the conventional nonvolatile memory device of FIG. 3, and FIG. 4B is a diagram illustrating a dispersion of a threshold voltage shift according to a width W of the charge storage layer in the conventional nonvolatile memory device of FIG. 4A.
Referring to FIGS. 4A and 4B, as the width W of the channel decreases during scale down, the threshold voltage may increase due to the bottleneck effect. When the width of the channel decreases, electrical charges passing through the channel may be trapped by the nano crystals 33NC, so that the threshold voltage may increase. The threshold voltage in each of the memory cells may increases to a different degree depending on the number of nano crystals 33NC included in the charge trap layer. This may be a problem when the width W of the channel decreases.
For example, when the width W of the channel is about 70 nm, the dispersion of the threshold voltage may be relatively small, but the dispersion of the threshold voltage in each of the memory cells may also be relatively small. When the width W of the channel is about 10 nm, the threshold voltage may increase, but the dispersion of the threshold voltage in each of the memory cells may be relatively large. Accordingly, errors may occur when the memory cell operates and there may be less reliability of the memory device. There may be a limitation in the relatively high integration of the memory device having divided memory layers, and thus, a more highly integrated memory device may be required.